Name
Abstract | ||
|---|---|---|
We developed test data compression scheme for scan-based BIST, aiming to compress test stimuli and responses by more than 100 times. As scan-BIST architecture, we adopt BIST-Aided Scan Test (BAST), and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 100x compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1093/ietisy/e91-d.3.726 | IEICE Transactions |
Keywords | Field | DocType |
scan-based bist,address partitioning,test data,lfsr pre-shifting,test data compression,test data compression scheme,compression rate,scan test,run-length compression,compress test stimulus,scan-based bist aiming,fault coverage,shift operator,chip,atpg | Fault coverage,Computer science,Real-time computing,Artificial intelligence,Computer hardware,Very-large-scale integration,Built-in self-test,Computer vision,Automatic test pattern generation,Data compression ratio,Test data,Data compression,Test compression | Journal |
Volume | Issue | ISSN |
E91-D | 3 | 1745-1361 |
Citations | PageRank | References |
3 | 0.43 | 17 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masayuki Arai | 1 | 61 | 14.17 |
| Satoshi Fukumoto | 2 | 54 | 14.85 |
| Kazuhiko Iwasaki | 3 | 100 | 23.45 |
| Tatsuru Matsuo | 4 | 9 | 0.94 |
| Takahisa Hiraide | 5 | 43 | 2.97 |
| Hideaki Konishi | 6 | 51 | 3.24 |
| Michiaki Emori | 7 | 44 | 3.53 |
| Takashi Aikyo | 8 | 93 | 11.46 |