Takashi Aikyo - Citegraph

Author Info

Name	Affiliation	Papers
TAKASHI AIKYO	STARC, Yokohama, Kanagawa, Japan	24
Collaborators	Citations	PageRank
58	93	11.46
Referers	Referees	References
252	362	237

Search Limit

100362

Publications (24 rows)

Collaborators (58 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Generation Of Diagnostic Tests For Transition Faults Using A Stuck-At Atpg Tool	1	0.36	2012
Distribution-Controlled X-Identification For Effective Reduction Of Launch-Induced Ir-Drop In At-Speed Scan Testing	0	0.34	2011
A Study Of Capture-Safe Test Generation Flow For At-Speed Testing	0	0.34	2010
Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau.	0	0.34	2010
Small Delay Fault Model for Intra-Gate Resistive Open Defects	5	0.54	2009
An Adaptive Test for Parametric Faults Based on Statistical Timing Information	9	0.71	2009
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC	5	0.50	2009
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment	9	0.54	2009
A Novel Approach for Improving the Quality of Open Fault Diagnosis	5	0.49	2009
Diagnostic Test Generation For Transition Faults Using A Stuck-At Atpg Tool	13	0.66	2009
Estimation of Delay Test Quality and Its Application to Test Generation.	6	0.58	2008
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information	1	0.36	2008
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification	16	0.80	2008
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate	3	0.43	2008
Post-BIST Fault Diagnosis for Multiple Faults	0	0.34	2008
Timing-Aware Diagnosis for Small Delay Defects	4	0.45	2007
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines	5	0.49	2007
Effective Post-BIST Fault Diagnosis for Multiple Faults	1	0.39	2006
Test Data Compression Of 100x For Scan-Based Bist	6	0.51	2006
Issues on SOC testing in DSM area: embedded tutorial	0	0.34	2000
A test synthesis approach to reducing BALLAST DFT overhead	1	0.35	1997
ATREX: Design for Testability System for Mega Gate LSIs	0	0.34	1997
ASIC CAD system based on hierarchical design-for-testability	2	0.60	1990
An Automatic Test Generation System for Large Scale Gate Arrays	1	0.67	1986