Name
Abstract | ||
|---|---|---|
Estimating and optimizing worst-case execution time (WCET) is critical for hard real-time systems to ensure that different tasks can meet their respective deadlines. Recent work has shown that simple prefetching techniques such as the Next-N-Line prefetching can enhance both the average-case and worst-case performance; however, the improvement on the worst-case execution time is rather limited and inefficient. This paper studies a loop-based instruction prefetching approach, which can exploit the program control-flow information to intelligently prefetch instructions that are most likely needed. Our evaluation indicates that the loop-based instruction prefetching outperforms the Next-N-Line prefetching in both the worst-case and the average-case performance for real-time applications. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TC.2010.44 | IEEE Trans. Computers |
Keywords | Field | DocType |
real-time and embedded systems,loop-based instruction prefetching,cache storage,simple prefetching technique,cache memories.,worst-case execution time,worst-case performance,worst-case execution time reduction,next-n-line prefetching,loop-based instruction,prefetch instruction,program control structures,hard real-time systems,hard real-time system,cache memories,real-time application,program control-flow information,real-time systems,average-case performance,benchmark testing,embedded system,control flow,algorithm design and analysis,information analysis,cache memory,time measurement,hardware,pollution,real time systems,worst case execution time | Algorithm design,Worst-case execution time,Computer science,Parallel computing,Real-time computing,Exploit,Execution time,Instruction prefetch,Benchmark (computing) | Journal |
Volume | Issue | ISSN |
59 | 6 | 0018-9340 |
Citations | PageRank | References |
2 | 0.39 | 40 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yiqiang Ding | 1 | 40 | 7.36 |
| Wei Zhang | 2 | 163 | 11.75 |