Name
Abstract | ||
|---|---|---|
In this paper, we present a reconfigurable multimedia accelerator (RMA) weakly coupled to an application processor. RMA relies on explicit multithreading and streaming intrinsics to mitigate the effects of memory latency and efficient bandwidth requirements dictated by modem multimedia applications. RMA is designed in 65nm and operates at a working frequency of 200 MHz |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/SOCC.2008.4641529 | IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS |
Keywords | Field | DocType |
registers,kernel,computer architecture,memory latency,scheduling | Multithreading,Computer science,Scheduling (computing),Real-time computing,Electronic engineering,Application processor,Intrinsics,CAS latency,Kernel (linear algebra),Mobile radio,Bandwidth (signal processing),Multimedia,Embedded system | Conference |
ISSN | Citations | PageRank |
2164-1676 | 2 | 0.41 |
References | Authors | |
11 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Samar Yazdani | 1 | 3 | 1.81 |
| Joel Cambonie | 2 | 4 | 1.38 |
| Bernard Pottier | 3 | 91 | 19.77 |