Bernard Pottier - Citegraph

Author Info

Name	Affiliation	Papers
BERNARD POTTIER	Univ Bretagne Occidentale, UMR 3192, Lab STICC, CNRS, Brest, France	48
Collaborators	Citations	PageRank
86	91	19.77
Referers	Referees	References
233	735	315

Search Limit

100735

Publications (48 rows)

Collaborators (86 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Brown Planthopper Sensor Network Optimization Based On Climate And Geographical Factors Using Cellular Automata Technique	0	0.34	2021
Open Data for Environment Sensing: Crowdsourcing Geolocation Data.	0	0.34	2020
Maximum Lifetime Target Coverage in Wireless Sensor Networks	2	0.38	2020
BPH Sensor Network Optimization Based on Cellular Automata and Honeycomb Structure	0	0.34	2020
An Approach of Concurrent Communications for Distributed Sensing Networks.	0	0.34	2020
A Developing Method for Distributed Sensing Systems	0	0.34	2019
Cross-Layer Greedy position-based routing for multihop wireless sensor networks in a real environment.	1	0.35	2018
Cellular Simulation for Distributed Sensing over Complex Terrains.	0	0.34	2018
A federation of simulations based on cellular automata in cyber-physical systems.	0	0.34	2016
An Hierarchical Scheduled Algorithm for Data Dissemination in a Brown Planthopper Surveillance Network.	0	0.34	2016
Modeling the Connections of Dynamic Sensor Fields Based on BT-Graph.	0	0.34	2016
Modeling and Optimizing of Connections for Dynamic Sensor Fields Based on BT-Graph.	0	0.34	2016
Synchronous networks for bio-environmental surveillance based on cellular automata.	0	0.34	2016
A Synchronous Network for Brown Planthopper Surveillance Based on Hexagonal Cellular Automata.	0	0.34	2016
Wireless Sensor Networks and Satellite Simulation.	0	0.34	2015
Synchronous networks for insects surveillance.	0	0.34	2015
A Federated Approach for Simulations in Cyber-Physical Systems.	1	0.36	2015
Optimizing the Connection Time for LEO Satellite Based on Dynamic Sensor Field.	1	0.40	2015
Energy Efficient Approach for Surveillance Applications Based on Self Organized Wireless Sensor Networks	0	0.34	2015
Designing a brown planthoppers surveillance network based on wireless sensor network approach.	3	0.52	2013
Visitor-based application analysis methodology for early design space exploration	1	0.36	2012
Meta-simulation of large WSN on multi-core computers	1	0.49	2010
A holistic approach for tightly coupled reconfigurable parallel processors	6	0.43	2009
Coordinated concurrent memory accesses on a reconfigurable multimedia accelerator	1	0.38	2009
Guest editorial CAPA'08 Configurable computing: Configuring algorithms, processes, and architecture Issue II: Configuring hardware architecture	0	0.34	2009
Toolset for nano-reconfigurable computing	5	0.45	2009
Guest editorial CAPA'08 configurable computing: Configuring algorithms, processes, and architecture issue I: Configuring algorithms and processes	26	0.82	2009
Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder	0	0.34	2009
Application Capturing and Performance Estimation in an Holistic Design Environment	0	0.34	2009
A Heuristic (delta, D) Digraph to Interpolate between Hypercube and de Bruijn Topologies for Future On-Chip Interconnection Networks	0	0.34	2009
Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems	0	0.34	2008
Application Analysis for Parallel Processing	1	0.39	2008
FPGAs or Distributed Systems?	0	0.34	2008
Reconfigurable Multimedia Accelerator For Mobile Systems	2	0.41	2008
An Integrated Platform for Heterogeneous Reconfigurable Computing	4	0.38	2007
Coordinated concurrent memory accesses on a reconfigurable multimedia processor	0	0.34	2007
Massively Parallel Processor Architectures: A Co-design Approach	1	0.36	2007
Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques	1	0.38	2006
The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA	2	0.44	2006
Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit	0	0.34	2005
Compiler level integration of a portable CAD framework for reconfigurable circuits	0	0.34	2005
Co-Design of Massively Parallel Embedded Processor Architectures	9	0.67	2005
A LUT based Approach for High Level Synthesis on FPGAs	1	0.39	2002
Placing, Routing, and Editing Virtual FPGAs	9	0.78	2001
Object Oriented Approach for Modeling Digital Circuits	4	0.45	1999
A 6200 Model and Editor Based on Object Technology	1	0.53	1998
Flexible Parallel FPGA-Based Architectures with ArMe	1	0.37	1994
Efficient global computations on a processor network with programmable logic	7	1.17	1991