Title
Instruction Based Testbench Architecture, invited
Abstract
This paper presents the synthesizable test-bench architecture based on the defined instruction for standalone mode verification. The proposed test-bench performs fast emulation with low resource and increases flexibility and reusability with variable description of instructions. To prove the performance of our testbench, we verified IEEE 802.11a PHY baseband system and compare with co-sim mode and modified co-sim mode emulation.
Year
DOI
Venue
2005
10.1109/IWSOC.2005.76
IWSOC
Keywords
DocType
ISBN
proposed test-bench,fast emulation,standalone mode verification,low resource,variable description,co-sim mode,synthesizable test-bench architecture,modified co-sim mode emulation,testbench architecture,increases flexibility,phy baseband system
Conference
0-7695-2403-6
Citations 
PageRank 
References 
0
0.34
0
Authors
3
Name
Order
Citations
PageRank
Ho-seok Choi121.07
Seungbeom Lee2457.04
Sin-Chong Park38022.58