Name
Abstract | ||
|---|---|---|
Digital clock and recovery circuits (CDRs) have recently emerged as an alternative to their more classical analog counterparts. This paper seeks to elucidate the design challenges and trade-offs involved in the design of digital CDRs. The jitter performance metrics such as jitter generation, jitter transfer, and jitter tolerance are related to digital CDR parameters and design guidelines are provided. The impact of digital phase detector non-linearity and quantization error, the digitally-controlled oscillator frequency quantization error, and loop latency on a digital CDR performance is analyzed and demonstrated using accurate behavioral simulations. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/CICC.2011.6055346 | 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) |
Keywords | Field | DocType |
jitter,oscillators,network synthesis | Computer science,Clock domain crossing,Electronic engineering,Clock skew,Digital clock,Jitter,Phase detector,Quantization (signal processing),Time-to-digital converter,Data strobe encoding | Conference |
Citations | PageRank | References |
5 | 0.68 | 21 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mrunmay Talegaonkar | 1 | 123 | 15.61 |
| Rajesh Inti | 2 | 118 | 13.20 |
| Pavan Kumar Hanumolu | 3 | 554 | 84.82 |