| A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation. | 2 | 0.39 | 2018 |
| A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS. | 2 | 0.64 | 2018 |
| A 0.7V time-based inductor for fully integrated low bandwidth filter applications | 0 | 0.34 | 2017 |
| A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. | 1 | 0.36 | 2017 |
| A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. | 1 | 0.43 | 2017 |
| 29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. | 1 | 0.37 | 2017 |
| A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. | 12 | 0.69 | 2016 |
| 23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. | 1 | 0.36 | 2016 |
| High Frequency Buck Converter Design Using Time-Based Control Techniques | 11 | 1.12 | 2015 |
| 3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS | 6 | 0.81 | 2015 |
| Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers | 11 | 0.63 | 2015 |
| A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links | 1 | 0.37 | 2015 |
| A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS | 1 | 0.39 | 2015 |
| A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method | 4 | 0.49 | 2015 |
| 3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS | 5 | 0.71 | 2015 |
| 10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS | 5 | 0.72 | 2015 |
| A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement | 2 | 0.57 | 2014 |
| A 4.4–5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter | 0 | 0.34 | 2014 |
| A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop | 11 | 0.66 | 2014 |
| A 10–25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW | 0 | 0.34 | 2014 |
| A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. | 1 | 0.52 | 2012 |
| A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS. | 6 | 0.78 | 2012 |
| A 1.5GHz 1.35mW −112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity | 2 | 0.36 | 2012 |
| A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. | 31 | 2.09 | 2012 |
| Digital Clock And Data Recovery Circuit Design: Challenges And Tradeoffs | 5 | 0.68 | 2011 |
| A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery | 1 | 0.43 | 2011 |
