Name
Abstract | ||
|---|---|---|
Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing optimization and timing-driven physical synthesis. Existing work in the literature, however, computes both metrics in a non-incremental manner, i.e., after one or more changes are made in a previously-timed circuit, both metrics need to be recomputed from scratch, which is obviously undesirable for optimizing large circuits. The major contribution of this paper is to propose two novel techniques to compute both criticality and yield gradients efficiently and incrementally. In addition, while node and edge criticalities are addressed in the literature, this paper for the first time describes a technique to compute path criticalities. To further improve algorithmic efficiency, this paper also proposes a novel technique to update "chip slack" incrementally. Numerical results show our methods to be over two orders of magnitude faster than previous work. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1403375.1403652 | Proceedings of the conference on Design, automation and test in Europe |
Keywords | Field | DocType |
digital circuits,probability,algorithmic efficiency,chip,error detection and correction,statistical analysis,cmos technology,design optimization | Digital electronics,Algorithmic efficiency,Statistical static timing analysis,Computer science,Parallel computing,Real-time computing,Chip,Error detection and correction,CMOS,Criticality,Electronic circuit | Conference |
ISSN | Citations | PageRank |
1530-1591 | 22 | 0.89 |
References | Authors | |
14 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiong Jinjun | 1 | 801 | 86.79 |
| Vladimir Zolotov | 2 | 1367 | 109.07 |
| Chandu Visweswariah | 3 | 615 | 60.90 |