| Large Data Flow Graphs In Limited Gpu Memory | 0 | 0.34 | 2019 |
| Analysis and Optimization of fastText Linear Text Classifier. | 0 | 0.34 | 2017 |
| Sharing And Re-Use Of Statistical Timing Macro-Models Across Multiple Voltage Domains | 0 | 0.34 | 2016 |
| Practical statistical static timing analysis with current source models. | 2 | 0.37 | 2016 |
| Generation and use of statistical timing macro-models considering slew and load variability. | 0 | 0.34 | 2016 |
| Variation aware cross-talk aggressor alignment by mixed integer linear programming | 3 | 0.40 | 2015 |
| Order statistics for correlated random variables and its application to at-speed testing | 3 | 0.39 | 2013 |
| Reversible statistical max/min operation: concept and applications to timing | 6 | 0.45 | 2012 |
| Testability-Driven Statistical Path Selection | 18 | 0.83 | 2012 |
| Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator | 7 | 0.49 | 2012 |
| Timing analysis with nonseparable statistical and deterministic variations | 4 | 0.74 | 2012 |
| Path criticality computation in parameterized statistical timing analysis | 5 | 0.46 | 2011 |
| Transistor sizing of custom high-performance digital circuits with parametric yield considerations | 7 | 0.49 | 2010 |
| Statistical multilayer process space coverage for at-speed test | 15 | 0.70 | 2009 |
| Optimal test margin computation for at-speed structural test | 3 | 0.40 | 2009 |
| Voltage binning under process variation | 12 | 0.82 | 2009 |
| Statistical Power Analysis For High-Performance Processors | 3 | 0.68 | 2009 |
| Pre-ATPG path selection for near optimal post-ATPG process space coverage | 6 | 0.49 | 2009 |
| Statistical ordering of correlated timing quantities and its application for path ranking | 1 | 0.35 | 2009 |
| Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power | 2 | 0.40 | 2008 |
| Statistical path selection for at-speed test | 29 | 1.12 | 2008 |
| Static timing: Back to our roots | 11 | 0.73 | 2008 |
| Incremental criticality and yield gradients | 22 | 0.89 | 2008 |
| Optimal margin computation for at-speed test | 10 | 0.61 | 2008 |
| Variation-aware performance verification using at-speed structural test and statistical timing | 27 | 1.40 | 2007 |
| Robust Extraction of Spatial Correlation | 131 | 8.15 | 2007 |
| Criticality computation in parameterized statistical timing | 41 | 1.65 | 2006 |
| Circuit optimization using statistical static timing analysis | 41 | 2.26 | 2005 |
| Optimization objectives and models of variation for statistical gate sizing | 3 | 0.44 | 2005 |
| Pessimism reduction in crosstalk noise aware STA | 14 | 0.80 | 2005 |
| Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions | 119 | 5.60 | 2005 |
| Delay noise pessimism reduction by logic correlations | 10 | 0.74 | 2004 |
| Static timing analysis using backward signal propagation | 6 | 0.56 | 2004 |
| Optimal placement of power supply pads and pins | 10 | 0.63 | 2004 |
| A stochastic approach To power grid analysis | 27 | 1.31 | 2004 |
| A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification | 4 | 0.79 | 2004 |
| Statistical timing analysis using bounds and selective enumeration. | 1 | 0.36 | 2003 |
| Statistical Clock Skew Analysis Considering Intra-Die Process Variations | 36 | 2.00 | 2003 |
| SOI Transistor Model for Fast Transient Simulation | 7 | 0.84 | 2003 |
| Static Electromigration Analysis for Signal Interconnects | 1 | 0.46 | 2003 |
| Statistical timing analysis for intra-die process variations with spatial correlations | 178 | 13.99 | 2003 |
| Statistical delay computation considering spatial correlations | 63 | 5.53 | 2003 |
| Vectorless Analysis of Supply Noise Induced Delay Variation | 30 | 2.46 | 2003 |
| Post-route gate sizing for crosstalk noise reduction | 14 | 0.88 | 2003 |
| Statistical Timing Analysis Using Bounds | 26 | 3.78 | 2003 |
| Computation and Refinement of Statistical Bounds on Circuit Delay | 49 | 8.77 | 2003 |
| A precorrected-FFT method for simulating on-chip inductance | 0 | 0.34 | 2002 |
| Inductance model and analysis methodology for high-speed on-chip interconnect | 5 | 0.56 | 2002 |
| Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model | 17 | 0.89 | 2002 |
| Worst case clock skew under power supply variations | 10 | 0.75 | 2002 |
