Name
Abstract | ||
|---|---|---|
Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the user's design which allow the system to be monitored and updated at runtime. An assortment of logic is added before synthesis to allow variable buffering, assertion checking, and automatic breakpointing. Low-level clock control and access to off-chip storage is managed by a custom hardware operating system. Through the addition of these features, a system can be debugged directly on the hardware, bypassing simulation and reducing iterations through the design flow. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1085130.1085145 | AADEBUG |
Keywords | Field | DocType |
automatic breakpointing,design flow,bypassing simulation,integrated debugging environment,reprogrammable hardware system,reprogrammble hardware system,custom hardware operating system,assertion checking,variable buffering,low-level clock control,high level,debugging,design,register transfer level,operating system,simulation,verification,chip | Inductive logic programming,Design for testing,Hardware compatibility list,Computer science,Custom hardware,Assertion,Design flow,High-level verification,Computer hardware,Debugging | Conference |
ISBN | Citations | PageRank |
1-59593-050-7 | 6 | 0.63 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kevin Camera | 1 | 61 | 20.82 |
| Hayden K.-H. So | 2 | 247 | 36.22 |
| Robert W. Brodersen | 3 | 1857 | 401.31 |