Name
Abstract | ||
|---|---|---|
In this work, we propose to develop and to combine in a same tool functional verification and robustness analysis of IP cores. The overall purpose of this methodology unifying functional verification and robustness analysis is to help designers in getting more quickly “first right time” hardened IP designs. Indeed, re-using the results of the functional verification analysis, i.e. mutation score, will help us to analyze more quickly the IP robustness. In this paper, we discuss about the synthesizable Mutation Function performing the transient fault injection. We focus on its efficiency to model realistic transient faults and to fit with the already existing Aligator platform performing the functional verification analysis of digital IP. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/DDECS.2011.5783046 | Design and Diagnostics of Electronic Circuits & Systems |
Keywords | Field | DocType |
electronic engineering computing,formal verification,industrial property,logic design,Aligator platform,IP robustness analysis,IP verification,functional verification analysis,intellectual property,mutation score,transient fault injection | Logic synthesis,Functional verification,Intelligent verification,Computer science,Field-programmable gate array,Real-time computing,Robustness (computer science),High-level verification,Computer engineering,Fault injection,Formal verification | Conference |
ISSN | ISBN | Citations |
2334-3133 | 978-1-4244-9755-3 | 2 |
PageRank | References | Authors |
0.48 | 4 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Hély | 1 | 89 | 21.91 |
| Vincent Beroulle | 2 | 86 | 21.86 |
| Feng Lu | 3 | 2 | 0.48 |
| José Ramón García Oya | 4 | 7 | 2.77 |
| Garcia, J.R.O. | 5 | 2 | 0.48 |