Name
Abstract | ||
|---|---|---|
Dual threshold voltage (dual-Vth) assignment is recognized as a useful technique to reduce the leakage power. However, as the process technology shrinks to the deep sub-micron regime, the negative bias temperature instability (NBTI) effect becomes a serious concern. The NBTI effect may cause the degradation of threshold voltage over a period of months or years. Since previous dual-Vth assignment techniques do not consider the NBTI effect, they often decrease the circuit lifetime. In this paper, we propose an NBTI-aware dual-Vth assignment algorithm. Our objective is not only to reduce the leakage power but also to maintain the lifetime of the circuit. By assigning independent candidate gates to high threshold voltage (HTV) simultaneously, in each benchmark circuit, our approach can achieve a better result with a smaller CPU time. Experimental data consistently show that our approach works well in practice. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCAS.2012.6272033 | ISCAS |
Keywords | Field | DocType |
leakage power reduction,dual threshold voltage assignment,integrated circuit design,nbti,negative bias temperature instability,logic gates,threshold voltage,degradation,algorithm design and analysis | Logic gate,Algorithm design,CPU time,Computer science,Leakage power,Electronic engineering,Integrated circuit design,Negative-bias temperature instability,Electrical engineering,Threshold voltage | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4673-0218-0 | 2 |
PageRank | References | Authors |
0.39 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wen-Pin Tu | 1 | 21 | 4.32 |
| Shih-Wei Wu | 2 | 2 | 0.72 |
| Shih-Hsu Huang | 3 | 203 | 38.89 |
| Mely Chen Chi | 4 | 44 | 6.78 |