Name
Abstract | ||
|---|---|---|
A new fault model, named propagation delay fault model, is proposed to test the gross gate delay defects modeled at each gate terminal and the distributed delay defects in the fault propagation paths. The proposed fault model assumes that the sum of the gross gate delay defect and the distributed delay defect are large enough to cause timing violation for all the paths passing through the fault site and the fault propagation path. Experimental results demonstrate that high fault coverage can be achieved in a reasonable amount of time and the test set size is comparable to the test set size generated for the transition fault model. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ASPDAC.2005.1466153 | ASP-DAC |
Keywords | Field | DocType |
logic circuits,new fault model,distributed delay defects,fault propagation paths,gross gate delay defect,transition fault model,test set,propagation delay fault,fault propagation path,timing violation,gate terminal,test set size,delays,fault diagnosis,high fault coverage,propagation delay fault model,gross gate delay defects,fault site,delay defect,proposed fault model,logic testing,fault model,yield,fault coverage,propagation delay,opc,dissection | Stuck-at fault,Delay calculation,Automatic test pattern generation,Propagation delay,Fault coverage,Computer science,Electronic engineering,Real-time computing,Elmore delay,Fault model,Fault indicator | Conference |
Volume | ISSN | ISBN |
1 | 2153-6961 | 0-7803-8736-8 |
Citations | PageRank | References |
3 | 0.46 | 17 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xijiang Lin | 1 | 687 | 42.03 |
| Janusz Rajski | 2 | 2460 | 201.28 |