Name
Abstract | ||
|---|---|---|
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states and some states are frequently revisited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and if sufficient conditions are met for them. Contrary to the previously proposed methods, where multitudes of fault simulations are required, the techniques described in this paper require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for circuits that have many revisited states. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/12.754997 | IEEE Trans. Computers |
Keywords | Field | DocType |
various test generator,static test sequence compaction,sequential circuit,small set,fast static compaction algorithms,test set,sequential circuit test vectors,fast algorithm,revisited state,fault simulation,test sequences traverse,fault simulation pass,benchmark testing,sequential analysis,compaction,sequential circuits | Automatic test pattern generation,Sequential logic,Computer science,Parallel computing,Circuit design,Algorithm,Real-time computing,Electronic circuit,Small set,Integrated circuit,Traverse,Test set | Journal |
Volume | Issue | ISSN |
48 | 3 | 0018-9340 |
Citations | PageRank | References |
28 | 1.42 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael S. Hsiao | 1 | 1467 | 132.13 |
| Elizabeth M. Rudnick | 2 | 867 | 76.37 |
| J. H. Patel | 3 | 4577 | 527.59 |