Name
Title | ||
|---|---|---|
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs |
Abstract | ||
|---|---|---|
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switches. In this paper, we study the usage of coarse-grain MTCMOS power switches for both logic circuits and SRAMs, and then propose corresponding methods of testing stuck-open power switches for each of them. For logic circuits, a specialized ATPG framework is proposed to generate a longest possible robust test while creating as many effective transitions in the switch-centered region as possible. For SRAMs, a novel test algorithm is proposed to exercise the worst-case power consumption and performance when stuck-open power switches exist. The experimental results based on an industrial MTCMOS technology demonstrate the advantage of our proposed testing methods on detecting stuck-open power switches for both logic circuits and SRAMs, when compared to conventional testing methods. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ICCAD.2010.5654118 | ICCAD |
Keywords | Field | DocType |
switches,cmos integrated circuits,logic circuits,integrated circuit testing,power-gating technique,idle devices,industrial mtcmos technology,ic leakage power consumption,testing method,coarse-grain multithreshold cmos,proposed testing method,leakage power consumption,coarse-grain mtcmos design,coarse-grain mtcmos designs,integrated circuit design,conventional testing method,atpg framework,stuck-open power,effective power-gating technique,stuck-open power switches,mtcmos power,mtcmos power switches,worst-case power consumption,logic circuit,coarse-grain mtcmos power,monte carlo,scheduling,automatic test pattern generation,test methods,robustness | Automatic test pattern generation,Logic gate,Test algorithm,Scheduling (computing),Computer science,Electronic engineering,CMOS,Real-time computing,Robustness (computer science),Integrated circuit design,Power consumption | Conference |
ISSN | ISBN | Citations |
1092-3152 | 978-1-4244-8193-4 | 2 |
PageRank | References | Authors |
0.40 | 16 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Szu-Pang Mu | 1 | 12 | 2.00 |
| Yi-Ming Wang | 2 | 2 | 0.40 |
| Hao-Yu Yang | 3 | 27 | 4.88 |
| Mango C.-T. Chao | 4 | 48 | 7.38 |
| Shi-Hao Chen | 5 | 30 | 6.08 |
| Chih-Mou Tseng | 6 | 8 | 1.35 |
| Tsung-Ying Tsai | 7 | 25 | 3.18 |