Mango C.-T. Chao - Citegraph

Author Info

Name	Affiliation	Papers
MANGO C.-T. CHAO	Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan	17
Collaborators	Citations	PageRank
49	48	7.38
Referers	Referees	References
156	382	209

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100382

Publications (17 rows)

Collaborators (49 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Layout-Based Dual-Cell-Aware Tests	0	0.34	2019
A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement.	0	0.34	2018
Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators.	6	0.50	2016
Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax.	0	0.34	2016
Predicting Vt mean and variance from parallel Id measurement with model-fitting technique	1	0.40	2016
Power-Up Sequence Control for MTCMOS Designs	6	0.53	2013
Alternate hammering test for application-specific DRAMs and an industrial case study	8	0.73	2012
Testing Methodology of Embedded DRAMs	3	0.46	2012
Detecting stability faults in sub-threshold SRAMs	0	0.34	2011
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes	3	0.39	2010
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs	2	0.40	2010
Power-switch routing for coarse-grain MTCMOS technologies	3	0.41	2009
Fault models for embedded-DRAM macros	7	0.68	2009
Testing Methodology Of Embedded Drams	3	0.42	2008
A hybrid scheme for compacting test responses with unknown values	2	0.37	2007
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors	4	0.41	2006
Coverage loss by using space compactors in presence of unknown values	0	0.34	2006

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