Name
Abstract | ||
|---|---|---|
This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1587/transfun.E96.A.1579 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
SRAM, soft error rate (SER), multiple cell upset (MCU), neutron particle, twin well, triple well | NMOS logic,Cmos process,Static random-access memory,Upset,Microcontroller,Sram cell,Macro,Mathematics,Embedded system | Journal |
Volume | Issue | ISSN |
E96A | 7 | 0916-8508 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shusuke Yoshimoto | 1 | 30 | 12.56 |
| Shunsuke Okumura | 2 | 63 | 12.54 |
| Koji Nii | 3 | 223 | 44.78 |
| Hiroshi Kawaguchi | 4 | 395 | 91.51 |
| Masahiko Yoshimoto | 5 | 0 | 0.34 |