Name
Abstract | ||
|---|---|---|
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors applied when the circuit operates as a sequential circuit, without using scan. These sequences can be applied at-speed, i.e., at the normal circuit clock speed. The objectives set for choosing the lengths of the functional sequences are to increase the number of vectors applied at-speed, and to reduce the number of settings of functional sequence lengths, without compromising the fault coverage achieved. The experimental results presented demonstrate that compared to earlier methods, the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ICCAD.2000.896514 | ICCAD |
Keywords | Field | DocType |
sequential circuit,higher fault coverage,benchmark circuit,normal circuit clock speed,bist scheme,earlier method,at-speed test,fault coverage,functional sequence length,functional sequence,inductance,sequential circuits,vlsi | Boundary scan,Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,Scan chain,Algorithm,Electronic engineering,Real-time computing,Very-large-scale integration,Clock rate,Built-in self-test | Conference |
ISBN | Citations | PageRank |
0-7803-6448-1 | 8 | 0.55 |
References | Authors | |
6 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yan Huang | 1 | 568 | 44.91 |
| I. Pomeranz | 2 | 1265 | 105.92 |
| S. M. Reddy | 3 | 8 | 0.55 |
| J. Rajski | 4 | 985 | 63.36 |