Name
Abstract | ||
|---|---|---|
This paper proposes a novel iterative remapping approach for area reduction while still respecting the timing constraints of the design specification. The use of complex gates can potentially reduce cell area, but they have to be chosen wisely to preserve timing constraints while remapping. Commercial tools for logic synthesis work better with simple cells and are not fully capable of taking advantage of complex cells; the strategy proposed herein is aimed to better exploit complex cells during technology mapping. The proposed iterative remapping approach can exploit a larger amount of logic gates, reducing global circuit area and respecting global timing constraints. Experiments show area improvement of 8% on average and up to 15% for a subset of combinational mapped circuits of IWLS 2005 benchmarks. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISVLSI.2013.6654639 | VLSI |
Keywords | Field | DocType |
combinational circuits,iterative methods,logic design,logic gates,timing circuits,IWLS 2005 benchmarks,cell area,combinational mapped circuits,complex cells,complex gates,design specification,global circuit area,global timing constraints,iterative remapping approach,logic gates,logic synthesis,technology mapping,complex gates,digital circuit,local optimization,resynthesis,technology mapping,timing constraints | Logic synthesis,Digital electronics,Logic gate,Computer science,Iterative method,Algorithm,Combinational logic,Local search (optimization),Design specification,Computer engineering,Benchmark (computing) | Conference |
ISSN | Citations | PageRank |
2159-3469 | 0 | 0.34 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lucas Machado | 1 | 0 | 1.01 |
| Mayler G. A. Martins | 2 | 88 | 10.08 |
| Vinicius Callegaro | 3 | 31 | 6.40 |
| Renato P. Ribas | 4 | 204 | 33.52 |
| André Inácio Reis | 5 | 134 | 21.33 |