Name
Abstract | ||
|---|---|---|
During post-silicon validation/debug of processors, it is common to alternate between two phases: processor execution and state dump. The state dump, where the entire processor state is dumped off-chip to a logic analyzer for further processing, is a major bottleneck. We present a technique for improving debug efficiency by reducing the volume of cache data dumped off-chip, while still capturing the complete state. The reduction is achieved by introducing hardware mechanisms to transmit only the portion of the cache that was updated since the last dump. We propose two design alternatives based on whether or not the processor is permitted to continue execution during the dump: Blocking Incremental Cache Dumping (BICD) and Non-blocking Incremental Cache Dumping (NICD). We observe a 64% reduction in overall cache lines dumped and the dump time reduces to an average of 16.8% and 0.0002% for BICD and NICD respectively. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/VLSISOC.2010.5642623 | PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP |
Keywords | Field | DocType |
engines,very large scale integration,hidden markov models,registers,chip,system on a chip,benchmark testing,data compression | Pipeline burst cache,Cache invalidation,Cache pollution,Cache,Computer science,Page cache,Cache algorithms,Cache coloring,Smart Cache,Operating system,Embedded system | Conference |
Citations | PageRank | References |
1 | 0.35 | 15 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Preeti Ranjan Panda | 1 | 786 | 89.40 |
| Anant Vishnoi | 2 | 7 | 0.80 |
| M. Balakrishnan | 3 | 518 | 72.63 |