Name
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/DATE.2008.4484643 | DATE |
Keywords | Field | DocType |
design optimization,power dissipation,design methodology,manufacturing,pareto optimization,phase locked loops,testing,energy management | Phase-locked loop,Power optimization,Computer science,CMOS,Design methods,Electronic engineering,Design flow,Control engineering,Jitter,Electronic circuit,Transistor | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Binkley | 1 | 36 | 3.61 |
| Helmut E. Graeb | 2 | 269 | 36.22 |
| Georges G. E. Gielen | 3 | 2036 | 254.40 |
| Jaijeet S. Roychowdhury | 4 | 152 | 22.23 |