Name
Abstract | ||
|---|---|---|
This paper proposes to use voltage-scaling (VS) and gate-sizing (GS) simultaneously for reducing power consumption without violating the timing constraints. We present algorithms for simultaneous VS and GS based on the Maximum-Weighted-Independent-Set problem. We describe the clock distribution of the circuit, completeness of gate library and discreteness of supply voltage, and discuss their effects on power optimization. Experimental results show that the average power reduction ranges from 23.3% to 56.9% over all tested circuits. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1145/368434.368668 | design automation conference |
Keywords | Field | DocType |
simultaneous voltage scaling,power reduction,gate sizing,power optimization,capacitance,low power electronics,independent set,high level synthesis,power dissipation,integrated circuit design | Power optimization,Computer science,High-level synthesis,Voltage,Real-time computing,Electronic engineering,Integrated circuit design,Sizing,Electronic circuit,AND gate,Low-power electronics | Conference |
ISBN | Citations | PageRank |
0-7803-5974-7 | 8 | 0.92 |
References | Authors | |
12 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chunhong Chen | 1 | 176 | 15.66 |
| Majid Sarrafzadeh | 2 | 3103 | 317.63 |