Chunhong Chen - Citegraph

Author Info

Name	Affiliation	Papers
CHUNHONG CHEN	Department of Electrical and Computer Engineering, University of Windsor, Ontario, Canada N9B 3P4. cchen@uwindsor.ca. CA	12
Collaborators	Citations	PageRank
13	176	15.66
Referers	Referees	References
347	208	123

Search Limit

100347

Publications (12 rows)

Collaborators (13 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Low Power Chien Search for BCH Decoder Using RT-Level Power Management	2	0.55	2011
Power efficient multi-stage CMOS rectifier design for UHF RFID tags	6	0.77	2011
Timing driven gate duplication	6	0.53	2004
Predicting potential performance for digital circuits	4	0.48	2002
Probability-based approach to rectilinear Steiner tree problems	2	0.43	2002
Budget Management with Applications	13	1.02	2002
Probabilistic analysis of rectilinear Steiner trees	0	0.34	2002
On gate level power optimization using dual-supply voltages	50	4.14	2001
Activity-driven clock design	42	3.28	2001
Power reduction by simultaneous voltage scaling and gate sizing	8	0.92	2000
Potential slack: an effective metric of combinational circuit performance	28	1.83	2000
Provably good algorithm for low power consumption with dual supply voltages	15	1.39	1999

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