Name
Abstract | ||
|---|---|---|
In this paper, a test generation based partial scan selection procedure is proposed. The procedure is able to achieve the same level of fault coverage as in a full scan design by scanning only a subset of the Pip-pops. New measures ore used to guide the Pip-pop selection during the procedure, The proposed procedure is applied to the ISCAS-89 and the ADDENDUM-99 benchmark; circuits. For all the circuits, it is possible to achieve the same fault coverage as that for full scan while scanning a portion of the flip-flops. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1145/307418.307545 | DATE |
Keywords | Field | DocType |
fault coverage,sequential circuits,benchmark testing,fault detection,feedback loop,automatic test pattern generation,sequential analysis | Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,Fault detection and isolation,Scan chain,Real-time computing,Feedback loop,Electronic circuit,Benchmark (computing) | Conference |
ISBN | Citations | PageRank |
1-58113-121-6 | 19 | 0.74 |
References | Authors | |
22 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xijiang Lin | 1 | 687 | 42.03 |
| Irith Pomeranz | 2 | 3829 | 336.84 |
| Sudhakar M. Reddy | 3 | 5747 | 699.51 |