Name
Abstract | ||
|---|---|---|
A 1.5-V 512-Mb DDR3 Synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C-IO minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/JSSC.2006.870808 | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Keywords | DocType | Volume |
calibration, DDR3 SDRAM, input capacitance, per-bank refresh, SCR type ESD, signal integrity, temperature sensor | Journal | 41 |
Issue | ISSN | Citations |
4 | 0018-9200 | 21 |
PageRank | References | Authors |
4.02 | 1 | 18 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dong Chan Park | 1 | 27 | 6.93 |
| H. Chung | 2 | 63 | 8.39 |
| Y.-S. Lee | 3 | 21 | 4.02 |
| Jungmoon Kim | 4 | 81 | 10.73 |
| B.-J. Lee | 5 | 104 | 19.31 |
| B.-J. Lee | 6 | 104 | 19.31 |
| M.-S. Chae | 7 | 21 | 4.02 |
| D.-H. Jung | 8 | 21 | 4.02 |
| S.-H. Choi | 9 | 21 | 4.02 |
| S. Seo | 10 | 21 | 4.35 |
| T.-S. Park | 11 | 21 | 4.02 |
| J.-H. Shin | 12 | 21 | 4.02 |
| J.-H. Cho | 13 | 21 | 4.02 |
| sungsik lee | 14 | 108 | 18.08 |
| K.-W. Song | 15 | 21 | 4.02 |
| K.-H. Kim | 16 | 21 | 4.02 |
| C. Kim | 17 | 21 | 4.02 |
| S.-I. Cho | 18 | 21 | 4.35 |