Title
A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications
Abstract
A fully asynchronous fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifically for a low power implementation. The novelty of this architecture lies in its high localization of components and pipelining with no need to share a global memory. High throughput is attained using large numbers of small, local components working in parallel. A derivation of the algorithm from the discrete Fourier transform is presented followed by a discussion of circuit design parameters specifically those relevant to space applications. A survey of this application specific architecture is included with a detailed look at the design of the complex-valued Booth multiplier to demonstrate the design methodology of this project. Finally, simulation results based on layout extractions are presented and an outline for future work is given.
Year
DOI
Venue
1998
10.1109/ASYNC.1998.666507
ASYNC
Keywords
Field
DocType
space application,high throughput,space applications,single chip low power,detailed look,complex-valued booth multiplier,circuit design parameter,high localization,design methodology,fft algorithm,low power space application,asynchronous implementation,low power implementation,application specific architecture,logic design,fixed point,fast fourier transforms,integrated circuit design,chip
Logic synthesis,Asynchronous communication,Pipeline (computing),Computer science,Parallel computing,Circuit design,Fast Fourier transform,Integrated circuit design,Discrete Fourier transform,Computer engineering,Booth's multiplication algorithm
Conference
ISBN
Citations 
PageRank 
0-8186-8392-9
3
1.14
References 
Authors
1
4
Name
Order
Citations
PageRank
Bruce W. Hunt131.14
Kenneth S. Stevens218525.65
Bruce W. Suter3142.30
Don S. Gelosh431.14