Name
Abstract | ||
|---|---|---|
A method for estimating the power consumption of multilevel combinational networks is introduced. The proposed method has as inputs the signal probabilities, the data correlations of the primary inputs and the structure of the circuit, and consists of two major steps: (i) the calculation of the switching activity on an individual gate and (ii) the calculation of the switching activity of any node of the network. The foregoing step includes the derivation of novel formulas for calculating the switching activity of basic gates. The latter step includes the development of an algorithm, which propagates the signal probabilities through the network and calculates the switching activity of any logic node. The proposed method provides accurate switching activity values performing their calculation in reduced time interval. The experimental results prove that the proposed method achieves significant reduction up to 50% in terms of multiplications compared to method of [6]. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1155/2001/31269 | VLSI DESIGN |
Keywords | Field | DocType |
low power design,switching activity estimation,power dissipation model,Markov chains,temporal and spatial correlation,CMOS combinational circuits | Computer science,Algorithm,Electronic engineering,Logic level,Data Correlations,Power consumption | Journal |
Volume | Issue | ISSN |
12 | 2 | 1065-514X |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| G. Theodoridis | 1 | 2 | 2.78 |
| S. Theoharis | 2 | 11 | 2.32 |
| Dimitrios Soudris | 3 | 369 | 58.95 |
| C. Goutis | 4 | 5 | 1.95 |