S. Theoharis - Citegraph

Author Info

Name	Affiliation	Papers
S. THEOHARIS	VLSI Design Laboratory, Department of Electrical and Computer Engineering, University of Patras, Rio 26500, Greece	6
Collaborators	Citations	PageRank
16	11	2.32
Referers	Referees	References
33	73	47

Publications (6 rows)

Collaborators (16 rows)

Referers (33 rows)

Referees (73 rows)

Title	Citations	PageRank	Year
Memory accesses reordering for interconnect power reduction in sum-of-products computations	3	0.38	2002
A fast and accurate delay dependent method for switching estimation of large combinational circuits	2	0.41	2002
A Fast and Accurate Method of Power Estimation for Logic Level Networks	0	0.34	2001
Low power synthesis of sum-of-products computation (poster session)	3	0.39	2000
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers	0	0.34	2000
An Efficient Probabilistic Method For Logic Circuits Using Real Delay Gate Model	3	0.46	1999

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