Name
Abstract | ||
|---|---|---|
The aim of this paper is to reduce the fault simulation effort required for the evaluation of test effectiveness in mixed-signal circuits. Exhaustive simulation of basic analog and mixed-signal structures in the presence of individual faults is used to identify potentially equivalent faults. Fault equivalence is finally evaluated based on the simulation of all faults in a case study--a DCDC (switched buck converter). The number of transistor stuck-on and stuck-off faults that need to be simulated is reduced to 31% in the structures already processed by the proposed methodology. This approach is a significant contribution to make mixed-signal fault simulation possible as part of the production test preparation. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ATS.2011.19 | Asian Test Symposium |
Keywords | Field | DocType |
mixed-signal fault equivalence,mixed-signal structure,fault equivalence,mixed-signal circuit,fault simulation effort,equivalent fault,exhaustive simulation,individual fault,mixed-signal fault simulation,production test preparation,stuck-off fault,analog,fault model,testing,topology,neodymium,test,transistors,mixed signal,buck converter | Stuck-at fault,Fault coverage,Computer science,Real-time computing,Electronic engineering,Equivalence (measure theory),Mixed-signal integrated circuit,Electronic circuit,Buck converter,Fault model,Fault indicator | Conference |
ISSN | Citations | PageRank |
1081-7735 | 0 | 0.34 |
References | Authors | |
3 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nuno Guerreiro | 1 | 1 | 0.71 |
| Marcelino B. Santos | 2 | 129 | 20.76 |