Marcelino B. Santos

Author Info

Name	Affiliation	Papers
MARCELINO B. SANTOS	IST / INESC-ID, R. Alves Redol, 9, 1000-029 Lisboa, Portugal	43
Collaborators	Citations	PageRank
85	129	20.76
Referers	Referees	References
283	513	319

Search Limit

100513

Publications (43 rows)

Collaborators (85 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Fault-Tolerance In Field Programmable Gate Array With Dynamic Voltage And Frequency Scaling	0	0.34	2015
Fault-tolerance in FPGA focusing power reduction or performance enhancement	0	0.34	2015
Digital modular control of high frequency DC-DC converters.	1	0.35	2014
Implicit current DC-DC Digital Voltage-Mode Control	0	0.34	2014
Performance sensor for tolerance and predictive detection of delay-faults	1	0.36	2014
Aging Monitoring With Local Sensors In Fpga-Based Designs	1	0.35	2013
The influence of clock-gating on NBTI-induced delay degradation	1	0.35	2012
Aging-Aware Power or Frequency Tuning With Predictive Fault Detection.	5	0.44	2012
An ultra-low noise current source for magnetoresistive biosensors biasing	2	0.67	2012
On-Line Bist For Performance Failure Prediction Under Nbti-Induced Aging In Safety-Critical Applications	0	0.34	2011
Digital LQR control with Kalman Estimator for DC-DC Buck converter	4	0.55	2011
Analysis of a monolithic buck converter's pMOS switch during turn off.	0	0.34	2011
Mixed-Signal Fault Equivalence: Search and Evaluation	0	0.34	2011
Adaptive Error-Prediction Flip-Flop For Performance Failure Prediction With Aging Sensors	11	0.77	2011
Smart Control Of Internal Supply Voltage Spikes In A Low Voltage Dc-Dc Buck Converter	0	0.34	2011
Low-sensitivity to process variations aging sensor for automotive safety-critical applications	8	0.59	2010
Gate Driver Voltage Optimization For Multi-Mode Low Power Dc-Dc Conversion	0	0.34	2009
Built-in aging monitoring for safety-critical applications	6	0.59	2009
Delay-Fault Tolerance To Power Supply Voltage Disturbances Analysis In Nanometer Technologies	2	0.39	2009
Noise Minimization For Low Power Bandgap Reference And Low Dropout Regulator Cores	0	0.34	2009
Time Management For Low-Power Design Of Digital Systems	3	0.44	2008
Level Shifters And Dcvsl For A Low-Voltage Cmos 4.2-V Buck Converter	2	0.52	2008
Signal Integrity Enhancement in Digital Circuits	1	0.35	2008
Functional-oriented mask-based built-in self-test	0	0.34	2007
Built-In Self-Test Quality Assessment Using Hardware Fault Emulation In Fpgas	1	0.37	2004
A probabilistic method for the computation of testability of RTL constructs	8	0.58	2004
FPGAs BIST Evaluation	1	0.36	2004
Fault Simulation Using Partially Reconfigurable Hardware	3	0.40	2003
Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems	0	0.34	2003
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage	0	0.34	2002
Self-checking and fault tolerance quality assessment using fault sampling	2	0.57	2002
Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Control	1	0.36	2001
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level	7	0.58	2001
From system level to defect-oriented test: a case study	0	0.34	1999
Defect-oriented test quality assessment using fault sampling and simulation	6	0.57	1998
Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation	12	1.22	1996
VHDL fault simulation for defect-oriented test and diagnosis of digital ICs	3	0.54	1996
On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits	0	0.34	1994
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs	7	0.65	1994
Realistic Fault Analysis of CMOS Analog Building Blocks	1	0.41	1993
Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs	8	0.71	1993
Physical DFT for High Coverage of Realistic Faults	18	1.52	1992
On the design of a highly testable cell library	3	0.45	1992