Name
Abstract | ||
|---|---|---|
A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm2 die size and a 0.044-μm2 effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-VCC in order to avoid program disturbance issues. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/JSSC.2003.818143 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
CMOS memory circuits,NAND circuits,flash memories,integrated circuit layout,memory architecture,photolithography,1.8 V,2 Gbit,90 nm,CMOS NAND flash memory,CMOS STI process technology,KrF photolithography,NAND cell strings,bitline precharge level,block placement,chip architecture,critical layer patterning,die size minimization,effective cell,higher level integration,mass storage applications,on-cell current,one-sided row decoder,program disturbance avoidance,string select line | Journal | 38 |
Issue | ISSN | Citations |
11 | 0018-9200 | 5 |
PageRank | References | Authors |
2.31 | 3 | 13 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| June Lee | 1 | 5 | 2.31 |
| Sungsoo Lee | 2 | 21 | 6.62 |
| Oh-Suk Kwon | 3 | 34 | 5.38 |
| Kyeong-Han Lee | 4 | 6 | 2.73 |
| Dae-Seok Byeon | 5 | 78 | 11.94 |
| Inyoung Kim | 6 | 101 | 16.92 |
| Kyoung-Hwa Lee | 7 | 19 | 4.11 |
| Young-ho | 8 | 5 | 2.31 |
| Byung-Soon Choi | 9 | 5 | 2.64 |
| Jong Sik Lee | 10 | 74 | 18.95 |
| Wang-Chul Shin | 11 | 5 | 2.31 |
| Jeong-Hyuk Choi | 12 | 59 | 8.17 |
| Kang-Deog Suh | 13 | 56 | 22.19 |