Title
Evaluating yield and testing impact of sub-wavelength lithography
Abstract
Sub-wavelength lithography uses light waves that have a longer wavelength than the feature size that is being printed. Image distortions are an inevitable consequence of this situation, even after resolution enhancement techniques have been applied. This paper studies in detail how the image distortion in a fabricated IC can impact test and critical-area yield loss. Particularly, lithography simulation is performed on the desired pattern to predict the printed (distorted) pattern. The impact on critical-area yield loss is studied using both the desired pattern and the printed pattern. Similarly, the impact on test is studied using inductive fault analysis on both the desired pattern and the printed pattern. Even under the assumption of the best process conditions, experiment results indicate that the difference in misdirected test effort can be as large as 8.0% and the difference in the critical-area yield calculations is about 3.4% for a large design. The more accurate analysis requires a runtime increase of 5X on average.
Year
DOI
Venue
2010
10.1109/VTS.2010.5469576
VTS
Keywords
Field
DocType
integrated circuit testing,sub-wavelength lithography,integrated circuit reliability,yield evaluation,fault simulation,image distortions,critical-area yield loss,inductive fault analysis,testing impact,resolution enhancement techniques,lithography,light waves,printed pattern,yield modeling,and critical area,subwavelength lithography,lithography simulation,impact test,fabricated ic,image resolution,cmos integrated circuits,pattern analysis,very large scale integration,layout
Test effort,Computer science,Inductive fault analysis,Electronic engineering,CMOS,Lithography,Very-large-scale integration,Image resolution,Distortion,Wavelength
Conference
ISSN
ISBN
Citations 
1093-0167
978-1-4244-6649-8
4
PageRank 
References 
Authors
0.41
13
3
Name
Order
Citations
PageRank
Wing Chiu Tam11097.29
R. D. (Shawn) Blanton264466.70
Wojciech Maly31976352.57