Name
Abstract | ||
|---|---|---|
Three dimensional (3-D) technologies have come under the spotlight to overcome limitations of conventional two dimensional (2-D) microprocessor Implementations. However, the effect of 3-D integration with vertical Interconnects in arithmetic units design is not well discussed yet. In this paper, aiming at clarifying the effectiveness of the 3-D integrated technology in arithmetic units design, fine grain 3-D integrated arithmetic units that aggressively employ vertical interconnects are designed and evaluated. This paper also presents a design strategy for 3-D integrated arithmetic units which partitions a circuit into sub-circuits to fully exploit the benefit of 3-D technologies. The simulation results using practical through-silicon-vias (TSVs) show that the fine grain 3-D integrated arithmetic units with the proposed circuit partitioning policy have a potential to improve the performance of the future arithmetic units. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/3DIC.2009.5306566 | 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION |
Keywords | Field | DocType |
network analysis,adders,silicon,three dimensional,through silicon via,integrated circuit design,stacking | Design strategy,Adder,Microprocessor,Arithmetic,Implementation,Exploit,Integrated circuit design,Engineering,Network analysis,Stacking | Conference |
ISSN | Citations | PageRank |
2164-0157 | 3 | 0.44 |
References | Authors | |
18 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ryusuke Egawa | 1 | 109 | 28.68 |
| Jubee Taday | 2 | 3 | 0.44 |
| Hiroaki Kobayashi | 3 | 108 | 14.52 |
| Gensuke Gotoy | 4 | 3 | 0.44 |