Paper Info
Title
Variation-tolerant cache by two-layer error control codes
Abstract
In this paper, we explore a two-layer error control codes (ECC), which combines rectangular and Hamming product codes in an efficient way to address process and supply voltage variation in cache. Two-layer ECC employs simple rectangular codes for each cache line to detect error, while loading extra Hamming product codes check bits in the case of error detection; thus enabling process and supply voltage variation-tolerant cache design. Our analysis and experimental results shows that compared to complex 4-way 4EC5ED, two-layer ECC can increase Mean-Error-To-Failure by more than 2×, improve reliability by two order of magnitude under process variation, and reduce residual failure rate by one order of magnitude under supply voltage variation. Compared to simple 8-way SECDED, two-layer ECC shows a 28x-133x improvement in METF, and residual failure rate are improved furthermore.
Year
DOI
Venue
2013
10.1109/DFT.2013.6653600
DFT
Keywords
Field
DocType
process variation,mean-error-to-failure,supply voltage variation,cache storage,error detection codes,two-layer ecc,error detection,power supply circuits,fault-tolerant,supply voltage variation-tolerant cache design,error correction codes,cache,failure analysis,product codes,residual failure rate,vlsi,hamming codes,4-way 4ec5ed,hamming product codes check bits,rectangular product code,ecc,magnitude under process variation,cache line,reliability,rectangular codes,metf,two-layer error control codes
Hamming code,Forward error correction,Concatenated error correction code,Cache,Computer science,CPU cache,Turbo code,Real-time computing,Electronic engineering,Error detection and correction,Linear code
Conference
ISSN
ISBN
Citations 
1550-5774
978-1-4799-1583-5
2
PageRank 
References 
Authors
0.41
16
2
Name
Order
Citations
PageRank
Meilin Zhang1403.16
Paul Ampadu228528.55