Name
Title | ||
|---|---|---|
A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector. |
Abstract | ||
|---|---|---|
This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with U... |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCSI.2011.2173387 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Clocks,Tracking loops,Propagation delay,Detectors,Charge pumps,Logic gates,Switches | Dual loop,Linear phase,Logic gate,CMOS,Electronic engineering,Synchronous circuit,Clock skew,Jitter,Detector,Mathematics | Journal |
Volume | Issue | ISSN |
59 | 6 | 1549-8328 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yung Sern Tan | 1 | 0 | 1.35 |
| Kiat Seng Yeo | 2 | 365 | 63.72 |
| Chirn Chye Boon | 3 | 136 | 26.81 |
| Manh Anh Do | 4 | 176 | 24.95 |