| A 0.6 V 4 GS/s-56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS | 0 | 0.34 | 2022 |
| A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression | 0 | 0.34 | 2022 |
| A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with +10dBm in-Band IIP3 in Current-Mode and 1.7dB NF in Voltage-Mode. | 0 | 0.34 | 2022 |
| A 0.0078mm2 3.4mW Wideband Positive-feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting $\boldsymbol{G}_{\mathrm{m}}$ Boosting | 0 | 0.34 | 2022 |
| A 0.092-mm<sup>2</sup> 2–12-GHz Noise-Cancelling Low-Noise Amplifier With Gain Improvement and Noise Reduction | 0 | 0.34 | 2022 |
| An Equivalent-Time Sampling Millimeter-Wave Ultra-Wideband Radar Pulse Digitizer in CMOS | 0 | 0.34 | 2022 |
| A 20-80 MHz Continuously Tunable Gm-C Low-Pass Filter for Ultra-Low Power WBAN Receiver Front-End | 0 | 0.34 | 2021 |
| A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5–6-GHz WLAN Carrier Aggregation | 1 | 0.41 | 2021 |
| A 2.4–6 GHz Broadband GaN Power Amplifier for 802.11ax Application | 0 | 0.34 | 2021 |
| 6.7 A 1.75dB-NF 25mW 5GHz Transformer-Based Noise-Cancelling CMOS Receiver Front-End | 0 | 0.34 | 2021 |
| A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation | 0 | 0.34 | 2021 |
| A 0.024-mm2 45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz. | 0 | 0.34 | 2020 |
| A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS | 0 | 0.34 | 2020 |
| A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter | 0 | 0.34 | 2020 |
| Design of a Wideband Variable-Gain Amplifier With Self-Compensated Transistor for Accurate dB-Linear Characteristic in 65 nm CMOS Technology | 0 | 0.34 | 2020 |
| Compact Switched-Capacitor Power Detector With Frequency Compensation in 65-nm CMOS | 0 | 0.34 | 2020 |
| Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line | 0 | 0.34 | 2020 |
| Monolithically Integrated GaN+CMOS Logic Circuits Design and Electro-Thermal Analysis for High-Voltage Applications | 0 | 0.34 | 2020 |
| An Inverted Ring Oscillator Noise-Shaping Time-to-Digital Converter With In-Band Noise Reduction and Coherent Noise Cancellation | 1 | 0.36 | 2020 |
| A 0.044-mm 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB. | 3 | 0.44 | 2019 |
| A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS | 1 | 0.36 | 2019 |
| A 0.0071-mm 2 10.8ps pp -Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis | 1 | 0.38 | 2019 |
| Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique | 1 | 0.36 | 2019 |
| Design and Analysis of <inline-formula> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula>-Band On-Chip Modulator and Signal Source Based on Split-Ring Resonator | 0 | 0.34 | 2019 |
| A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications | 0 | 0.34 | 2019 |
| A 24/77 GHz Dual-Band Receiver for Automotive Radar Applications. | 0 | 0.34 | 2019 |
| A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications. | 2 | 0.42 | 2018 |
| D-Band Surface-Wave Modulator and Signal Source with 40 dB Extinction Ratio and 3.7mW Output Power in 65 nm CMOS. | 0 | 0.34 | 2018 |
| A W-Band Switch-Less Dicke Receiver for Millimeter-Wave Imaging in 65 nm CMOS. | 0 | 0.34 | 2018 |
| A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin. | 3 | 0.42 | 2018 |
| A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS. | 0 | 0.34 | 2018 |
| Pole-Converging Intrastage Bandwidth Extension Technique for Wideband Amplifiers. | 2 | 0.39 | 2017 |
| An on-chip integrated III–V / CMOS 125MSps 6-bit SAR ADC | 0 | 0.34 | 2016 |
| Cell-Based Variable-Gain Amplifiers With Accurate dB-Linear Characteristic in 0.18 µm CMOS Technology | 19 | 1.33 | 2015 |
| Editorial | 0 | 0.34 | 2014 |
| A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology. | 14 | 0.93 | 2014 |
| Design and Analysis of a 2.4 GHz Hybrid Type Automatic amplitude Control VCO with Forward noise Reduction. | 0 | 0.34 | 2014 |
| A case for leveraging 802.11p for direct phone-to-phone communications | 2 | 0.37 | 2014 |
| A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS | 3 | 0.58 | 2013 |
| A low-noise amplifier with continuously-tuned input matching frequency and output resonance frequency | 0 | 0.34 | 2013 |
| Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission | 7 | 0.58 | 2013 |
| Design of quarter-wavelength resonator filters with coupling controllable paths | 0 | 0.34 | 2012 |
| A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector. | 0 | 0.34 | 2012 |
| Implementations of signal-processing algorithms for OFDM systems | 1 | 0.37 | 2012 |
| A Low-Power Single-Phase Clock Multiband Flexible Divider | 6 | 0.66 | 2012 |
| A 100 GHz transformer-based varactor-less VCO with 11.2% tuning range in 65nm CMOS technology | 2 | 0.40 | 2012 |
| A low power low phase noise dual-band multiphase VCO | 1 | 0.37 | 2012 |
| A 3.1-8 GHz CMOS UWB front-end receiver | 0 | 0.34 | 2011 |
| An energy-aware CMOS receiver front end for low-power 2.4-GHz applications | 9 | 0.72 | 2010 |
| Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler | 19 | 1.81 | 2010 |
