Name
Abstract | ||
|---|---|---|
We describe two approaches for developing generic components in VHDL. The first approach uses pure VHDL abstractions. The second uses VHDL abstractions combined together with those of the scripting language Open PROMOL we have developed aiming at building generic components and component-based generators. Both approaches are based on the generic component model. Due to the usage of the monolithic, hierarchical and generative architectures within the model, its implementation ensures the key solutions, reduces the effect of the complexity of the problem, and increases productivity in IC design, respectively. We deliver a comparison of the approaches and describe the experiments we carried out. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1016/S0026-2692(01)00141-0 | Microelectronics Journal |
Keywords | Field | DocType |
Scripting language,Target language,Component-based VHDL generation,Generic component model,IP,Generic component design | Abstraction,Programming language,Computer science,Electronic system-level design and verification,VHDL,Hardware description language,Scripting language | Conference |
Volume | Issue | ISSN |
33 | 3 | Microelectronics Journal |
ISBN | Citations | PageRank |
0-7695-0993-2 | 2 | 0.49 |
References | Authors | |
12 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vytautas Stuikys | 1 | 102 | 17.07 |
| giedrius ziberkas | 2 | 11 | 2.39 |
| Robertas Damasevicius | 3 | 281 | 62.75 |
| giedrius majauskas | 4 | 2 | 0.49 |