Name
Abstract | ||
|---|---|---|
Packet-based Networks-on-Chip (NoC) have emerged as the most viable candidates for the interconnect backbone of future Chip Multi-Processors (CMP). The flit size (or width) is one of the fundamental design parameters within a NoC router, which affects both the performance and the cost of the network. Most studies pertaining to the NoC of general-purpose microprocessors adopt a certain flit width without any reasoning or explanation. In fact, it is not easy to pinpoint an optimal flit size, because the flit size is intricately intertwined with various aspects of the system. This paper aims to provide a guideline on how to choose an appropriate flit width. It will be demonstrated that arbitrarily choosing a flit width without proper investigation may have serious repercussions on the overall behavior of the system. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISVLSI.2013.6654614 | ISVLSI |
Keywords | Field | DocType |
noc router,flit size/width,network routing,link width optimization,microprocessor chips,networks-on-chip,logic design,optimal flit size,flit width,chip multiprocessors,network-on-chip,general purpose microprocessors,network on chip | Logic synthesis,Network routing,Network packet,Computer network,Network on a chip,Chip,Engineering,Throughput,Router,Interconnection,Embedded system | Conference |
ISSN | Citations | PageRank |
2159-3469 | 17 | 0.79 |
References | Authors | |
21 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Junghee Lee | 1 | 226 | 27.26 |
| Chrysostomos Nicopoulos | 2 | 835 | 50.37 |
| Sung Joo Park | 3 | 276 | 22.40 |
| madhavan swaminathan | 4 | 108 | 24.63 |
| Jongman Kim | 5 | 770 | 37.65 |