| Low-Cost Online Convolution Checksum Checker | 1 | 0.38 | 2022 |
| A Hardware-Assisted Heartbeat Mechanism for Fault Identification in Large-Scale IoT Systems | 1 | 0.37 | 2022 |
| Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching | 1 | 0.37 | 2021 |
| Autonomous Application of Netlist Transformations inside Lagrangian Relaxation-based Optimization | 0 | 0.34 | 2021 |
| The Mesochronous Dual-Clock FIFO Buffer | 1 | 0.36 | 2020 |
| Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering | 0 | 0.34 | 2020 |
| SmartFork: Partitioned Multicast Allocation and Switching in Network-on-Chip Routers | 0 | 0.34 | 2020 |
| RISC-V2: A Scalable RISC-V Vector Processor | 0 | 0.34 | 2020 |
| 2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD) | 0 | 0.34 | 2020 |
| Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation | 0 | 0.34 | 2020 |
| Error-Shielded Register Renaming Sub-System For A Dynamically Scheduled Out-Of-Order Core | 0 | 0.34 | 2019 |
| Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage | 0 | 0.34 | 2019 |
| Multi-Armed Bandits for Autonomous Timing-driven Design Optimization | 0 | 0.34 | 2019 |
| Automatic Generation of Peak-Power Traffic for Networks-on-Chip. | 1 | 0.35 | 2019 |
| A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. | 5 | 1.32 | 2018 |
| Hardware-Based Online Self-Diagnosis for Faulty Device Identification in Large-Scale IoT Systems | 1 | 0.35 | 2018 |
| Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs. | 0 | 0.34 | 2018 |
| Fast Estimations of Failure Probability Over Long Time Spans. | 0 | 0.34 | 2018 |
| A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems. | 0 | 0.34 | 2017 |
| A Dual-Clock Multiple-Queue Shared Buffer. | 2 | 0.37 | 2017 |
| HoPE: Hot-Cacheline Prediction for Dynamic Early Decompression in Compressed LLCs. | 2 | 0.36 | 2017 |
| Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling | 0 | 0.34 | 2017 |
| HARPA: Tackling physically induced performance variability. | 0 | 0.34 | 2017 |
| BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers. | 2 | 0.41 | 2017 |
| Networks-on-Chip With Double-Data-Rate Links. | 3 | 0.39 | 2017 |
| PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels. | 4 | 0.42 | 2016 |
| Powermax: an automated methodology for generating peak-power traffic in networks-on-chip | 0 | 0.34 | 2016 |
| ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing. | 7 | 0.43 | 2016 |
| An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures. | 3 | 0.43 | 2016 |
| DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors | 3 | 0.38 | 2016 |
| A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. | 6 | 0.45 | 2016 |
| Crossover: Clock Domain Crossing Under Virtual-Channel Flow Control | 0 | 0.34 | 2016 |
| HARPA: Solutions for dependable performance under physically induced performance variability | 2 | 0.39 | 2015 |
| Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors | 0 | 0.34 | 2015 |
| Timing-resilient Network-on-Chip architectures | 1 | 0.35 | 2015 |
| Subtleties of Run-Time VirtualAddress Stacks | 0 | 0.34 | 2015 |
| ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip | 4 | 0.46 | 2015 |
| Size-Aware Cache Management for Compressed Cache Architectures | 4 | 0.38 | 2015 |
| Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion | 1 | 0.39 | 2014 |
| Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression | 3 | 0.38 | 2014 |
| Exploration of system availability during software-based self-testing in many-core systems under test latency constraints | 3 | 0.38 | 2014 |
| Hardware-Assisted Intrusion Detection by Preserving Reference Information Integrity | 0 | 0.34 | 2013 |
| ECM: Effective Capacity Maximizer for high-performance compressed caching | 10 | 0.53 | 2013 |
| Do we need wide flits in Networks-on-Chip? | 17 | 0.79 | 2013 |
| TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era. | 3 | 0.39 | 2013 |
| DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems. | 6 | 0.46 | 2013 |
| IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures | 5 | 0.51 | 2013 |
| Sharded Router: A novel on-chip router architecture employing bandwidth sharding and stealing. | 1 | 0.35 | 2013 |
| A highly robust distributed fault-tolerant routing algorithm for NoCs with localized rerouting | 4 | 0.38 | 2012 |
| A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures | 9 | 0.46 | 2012 |
