Paper Info
Title
Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays
Abstract
This paper develops a built-in self-detection/correction (BISDC) architecture for motion estimation computing arrays (MECAs). Based on the error detection/correction concepts of biresidue codes, any single error in each processing element in an MECA can be effectively detected and corrected online using the proposed BISD and built-in self-correction circuits. Performance analysis and evaluation demonstrate that the proposed BISDC architecture performs well in error detection and correction with minor area overhead and timing penalty.
Year
DOI
Venue
2010
10.1109/TVLSI.2008.2009452
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
Field
DocType
biresidue code,motion estimation computing array,motion estimation computing arrays,correction concept,built-in self-detection architecture,residue codes,built-in self-correction (bisc),error detection,biresidue codes,logic arrays,correction architecture,motion estimation,built-in self-correction circuit,proposed bisdc architecture,minor area overhead,video coding,motion estimation computing array (meca),area overhead,timing penalty,proposed bisd,built-in self-detection (bisd),built-in self-detection,error correction,built-in self-correction circuits,single error,corrected online,degradation,error detection and correction,design for testability,very large scale integration,fault tolerance,computer architecture,system testing
Design for testing,System testing,Computer science,Electronic engineering,Real-time computing,Error detection and correction,Motion estimation,Electronic circuit,Very-large-scale integration,Integrated circuit,Built-in self-test
Journal
Volume
Issue
ISSN
18
2
1063-8210
Citations 
PageRank 
References 
2
0.37
6
Authors
3
Name
Order
Citations
PageRank
Chun-Lung Hsu15914.53
Chang-Hsin Cheng293.13
Yu Liu330.72