Paper Info
Title
A Bit-Serial Reconfigurable Vlsi Based On A Multiple-Valued X-Net Data Transfer Scheme
Abstract
A multiple-valued data transfer scheme using X-net is proposed to realize a compact bit-serial reconfigurable VLSI (BS-RVLSI). In the multiple-valued data transfer scheme using X-net, two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each "X" intersection. One cell composed of a logic block and a switch block is connected to four adjacent cross points by four one-bit switches so that the complexity of the switch block is reduced to 50% in comparison with the cell of a BS-RVLSI using an eight nearest-neighbor mesh network (8-NNM). In the logic block, threshold logic circuits are used to perform threshold operations, and then their binary dual-rail voltage outputs enter a binary logic module which can be programmed to realize an arbitrary two-variable binary function or a bit-serial adder. As a result, the configuration memory count and transistor count of the proposed multiple-valued cell are reduced to 34% and 58%, respectively, in comparison with those of an equivalent CMOS cell. Moreover, its power consumption for an arbitrary 2-variable binary function becomes 67% at 800 MHz Under the condition of the same delay time.
Year
DOI
Venue
2013
10.1587/transinf.E96.D.1449
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
Keywords
Field
DocType
multiple-valued data transfer scheme, X-net, multiple-valued current-mode logic, MOS current-mode logic, fine-grain reconfigurable VLSI
Logic gate,Adder,Computer science,Real-time computing,Artificial intelligence,Very-large-scale integration,Binary number,Transistor count,Topology,Pattern recognition,CMOS,Logic block,Binary data
Journal
Volume
Issue
ISSN
E96D
7
1745-1361
Citations 
PageRank 
References 
4
0.48
10
Authors
2
Name
Order
Citations
PageRank
Xu Bai1379.94
Michitaka Kameyama243199.93