Name
Title | ||
|---|---|---|
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor |
Abstract | ||
|---|---|---|
Reducing program size is a critical issue in many embedded systems which require more functionalities without increasing the memory size. One of the approaches is to adopt a mixed-width instruction set architecture (ISA) which usually has an instruction set in general formats (usually 32-bit long) as normal instruction set and an instruction set in shorter format(usually 16-bit long) with limited opcodes and set of registers. Traditionally, a code segment can been coded in only one format, no multiple formats interleaved. However, more and more processors use instruction encoding to indicate the length of each individual instruction and take mixed-width ISA into instruction-level granularity. For this kind of ISAs, the number of instructions can be encoded in shorter format is highly dependent on the limited set of registers that can be accessed by shorter format instructions. In this paper, we present a register allocation and assignment algorithm based on graph coloring, which uses a heuristic model to find out which virtual variables in program should be assigned into the set of registers accessible by shorter instructions. The simulation results show that 63.34%of the instructions can be translated into shorter format on average. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/CSE.2009.100 | CSE (2) |
Keywords | Field | DocType |
mixed-width instruction set architecture processor,heuristic model,instruction setin general format,mixed-width instruction setarchitecture,register allocation,assignment algorithm,microprocessor chips,compiler,eachindividual instruction,code size reduction,limited opcodes,embedded processor,graph coloring register allocation,normalinstruction set,graph colouring,shorter format,instruction-level granularity,mixed-width isa,memory size,instruction sets,program size,code size,optimising compilers,limited set ofregisters,embedded systems,mixed-width isa processor,instruction encoding,shorter formatinstructions,instruction set architecture,registers,graph coloring,diamond like carbon,switches,encoding,resource management,data mining,limit set,embedded system,algorithm design and analysis | Opcode,Algorithm design,Register allocation,Instruction set,Computer science,Parallel computing,Algorithm,Compiler,Code (cryptography),Encoding (memory),Graph coloring | Conference |
Volume | ISBN | Citations |
2 | 978-0-7695-3823-5 | 0 |
PageRank | References | Authors |
0.34 | 7 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jyh-Shian Wang | 1 | 0 | 0.34 |
| I-Wei Wu | 2 | 46 | 5.18 |
| Yu-Sheng Chen | 3 | 63 | 8.02 |
| Jean Jyh-Jiun Shann | 4 | 65 | 10.46 |
| Wei-Chung Hsu | 5 | 719 | 58.87 |