Name
Abstract | ||
|---|---|---|
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown how properties relevant for scheduling and verification of specification models such as Boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets can be represented in the FunState model of computation. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in the form of a periodic graph. The feasibility of the novel approach is shown with an asynchronous transfer mode switch example. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/92.931229 | IEEE Trans. VLSI Syst. |
Keywords | DocType | Volume |
scheduling mechanism,high-level synthesis,petri net,index terms— formal verification,state machine,specification model,in- ternal specification model,model of computation,internal design model,internal design representation,funstate model,cyclostatic dataflow,boolean dataflow,state transition,synchronous dataflow,symbolic scheduling,switches,hardware,finite state machines,scheduling,dynamic scheduling,high level synthesis,formal specification,computer networks,formal verification,indexing terms,petri nets,asynchronous transfer mode,periodic graph,functional programming,computational modeling | Journal | 9 |
Issue | ISSN | Citations |
4 | 1063-8210 | 47 |
PageRank | References | Authors |
2.45 | 41 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Karsten Strehl | 1 | 134 | 10.86 |
| Lothar Thiele | 2 | 14025 | 957.82 |
| Matthias Gries | 3 | 365 | 29.67 |
| Dirk Ziegenbein | 4 | 118 | 11.80 |
| Rolf Ernst | 5 | 2633 | 252.90 |
| Jürgen Teich | 6 | 2886 | 273.54 |