Name
Title | ||
|---|---|---|
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells |
Abstract | ||
|---|---|---|
Leakage estimation is an important step in nano-scale technology digital design flows. While reliable data exist on leakage trends with bulk CMOS technology scaling in stand-alone devices and circuits, there is a lack of public domain results on the effect of scaling on leakage power consumption for a complete standard cell set. We present an analysis on a standard cell library applying a logic-level estimation model, supported by SPICE BSIM4 comparison. The logic-level model speedup over SPICE is 10^3 with average accuracy below 1% error. We therefore explore the effects of scaling on the whole standard cell set with respect to different leakage mechanisms (sub-threshold, body, gate) and to input pattern dependence. While body leakage appears to be dominant, sub-threshold leakage is expected to increase more than other components with scaling. Detailed data of the whole analysis are reported for use in further research on leakage aware digital design. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1016/j.mejo.2013.10.013 | Microelectronics Journal |
Keywords | Field | DocType |
bulk cmos technology scaling,nano-scale bulk,leakage aware digital design,complete standard cell set,leakage trend,cmos digital standard cell,standard cell library,leakage power consumption,sub-threshold leakage,body leakage,leakage estimation,different leakage mechanism,cmos,scaling,standard cell | Leakage (electronics),Spice,Design flow,CMOS,Electronic engineering,Standard cell,Engineering,Electronic circuit,Scaling,Speedup | Journal |
Volume | Issue | ISSN |
45 | 2 | 0026-2692 |
Citations | PageRank | References |
10 | 0.63 | 12 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zia Abbas | 1 | 13 | 4.74 |
| Mauro Olivieri | 2 | 385 | 36.09 |