| A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design | 1 | 0.40 | 2021 |
| Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores | 3 | 0.46 | 2021 |
| Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment | 0 | 0.34 | 2020 |
| SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing | 2 | 0.36 | 2020 |
| Quality Aware Selective ECC for Approximate DRAM. | 0 | 0.34 | 2019 |
| A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. | 2 | 0.44 | 2019 |
| Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. | 0 | 0.34 | 2019 |
| Full System Emulation Of Approximate Memory Platforms With Appropinquo | 0 | 0.34 | 2019 |
| Quality Aware Approximate Memory in RISC-V Linux Kernel | 0 | 0.34 | 2019 |
| The international race towards Exascale in Europe | 1 | 0.36 | 2019 |
| Approximate Memory Support for Linux Early Allocators in ARM Architectures. | 0 | 0.34 | 2018 |
| Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing. | 1 | 0.35 | 2018 |
| LEADER - Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits. | 0 | 0.34 | 2018 |
| AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space | 0 | 0.34 | 2018 |
| Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores | 1 | 0.39 | 2017 |
| The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. | 2 | 0.44 | 2017 |
| Optimal transistor sizing for maximum yield in variation-aware standard cell design. | 0 | 0.34 | 2016 |
| An Emulator for Approximate Memory Platforms Based on QEmu | 0 | 0.34 | 2016 |
| Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide | 0 | 0.34 | 2015 |
| Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops | 4 | 0.43 | 2015 |
| Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs | 4 | 0.55 | 2014 |
| A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs | 5 | 0.49 | 2014 |
| A Model-Based Methodology to Generate Code for Timer Units | 0 | 0.34 | 2014 |
| Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells | 10 | 0.63 | 2014 |
| A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems | 0 | 0.34 | 2014 |
| A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family | 3 | 0.37 | 2013 |
| First integration of MOSFET band-to-band-tunneling current in BSIM4 | 1 | 0.38 | 2013 |
| Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+) | 0 | 0.34 | 2013 |
| A general design methodology for synchronous early-completion-prediction adders in nano-CMOS DSP architectures | 1 | 0.35 | 2013 |
| Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications. | 0 | 0.34 | 2013 |
| Delay-Tolerant, Low-Power Protocols For Large Security-Critical Wireless Sensor Networks | 3 | 0.55 | 2012 |
| Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores. | 1 | 0.35 | 2011 |
| TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction. | 4 | 0.38 | 2010 |
| Adaptive idleness distribution for non-uniform aging tolerance in multiprocessor systems-on-chip | 8 | 0.63 | 2009 |
| A novel high-quality YUV-based image coding technique for efficient image storage in portable electronic appliances | 2 | 0.51 | 2008 |
| A new dynamic differential logic style as a countermeasure to power analysis attacks | 2 | 0.37 | 2008 |
| High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips | 9 | 0.59 | 2008 |
| A statistical model of logic gates for Monte Carlo simulation including on-chip variations | 1 | 0.38 | 2007 |
| Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units | 3 | 0.48 | 2007 |
| Design And Test Of A Novel Programmable Clock Generator Semi-Custom Core For Energy-Efficient Systems-On-Chips | 0 | 0.34 | 2005 |
| A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control | 13 | 0.87 | 2005 |
| Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique | 0 | 0.34 | 2005 |
| MPARM: Exploring the Multi-Processor SoC Design Space with SystemC | 150 | 5.58 | 2005 |
| A class of code compression schemes for reducing power consumption in embedded microprocessor systems | 21 | 0.99 | 2004 |
| A post-compiler approach to scratchpad mapping of code | 60 | 2.12 | 2004 |
| Bus-switch coding for reducing power dissipation in off-chip buses | 4 | 0.54 | 2004 |
| Power Efficiency of Application-Dependent Self-Configuring Pipeline Depth in DSP Microprocessors | 0 | 0.34 | 2003 |
| An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores | 1 | 0.38 | 2001 |
| An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors | 6 | 0.91 | 2001 |
| Semicustom Design of an IEEE 1394-Compliant Reusable IC Core | 4 | 0.59 | 2000 |
