Title
A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process.
Abstract
A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip ind...
Year
DOI
Venue
2010
10.1109/JSSC.2010.2075410
IEEE Journal of Solid-State Circuits
Keywords
Field
DocType
CMOS technology,Driver circuits,Multiplexing,Transceivers,Detectors,Receivers,Transmitters
Sense amplifier,Demultiplexer,Phase-locked loop,Transceiver,Clock recovery,Computer science,Electronic engineering,CMOS,Multiplexer,Electrical engineering,Low-power electronics
Journal
Volume
Issue
ISSN
45
12
0018-9200
Citations 
PageRank 
References 
37
3.76
7
Authors
9
Name
Order
Citations
PageRank
Koji Fukuda1396.03
Hiroki Yamashita28314.48
Goichi Ono36120.30
Ryo Nemoto4384.64
Eiichi Suzuki5373.76
Noboru Masuda6577.07
Takashi Takemoto79919.11
Fumio Yuki86410.51
Tatsuya Saito9385.32