Paper Info
Title
Orthogonal transpose-RAM cell array architecture with alternate bit-line to bit-line contact scheme
Abstract
An orthogonal RAM cell array architecture suitable for efficient transposing is proposed, and layout and simulation results are presented. The cell is developed to adopt folded bit-line sensing scheme area-efficiently. The proposed alternate bit-line to bit-line contact scheme in the orthogonal RAM cell array architecture leads to asymmetric bit-line sensing scheme and (i, 2i) bit-line transposing scheme, and results in fast response time of the sense amplifier and low power dissipation for restoring
Year
DOI
Venue
2001
10.1109/MTDT.2001.945222
MTDT
Keywords
Field
DocType
efficient transposing,cmos sense amplifiers,random-access storage,integrated circuit metallisation,orthogonal ram cell array,fast response time,orthogonal transpose-ram cell array,folded bit-line sensing scheme,asymmetric bit-line sensing scheme,low power dissipation,ram cell array layout,low-power electronics,proposed alternate bit-line,alternate bit-line to bit-line contact scheme,transposing scheme,bit-line transposing scheme,cellular arrays,alternate bit-line,sense amplifier,layout pattern,integrated circuit layout,simulation result,bit-line contact scheme,orthogonal ram cell array architecture,contact scheme,scheme area-efficiently,cmos memory circuits,orthogonal transpose ram,computer science,computer simulation,computer architecture,computational modeling,low power electronics,capacitance
Integrated circuit layout,Sense amplifier,Architecture,Transpose,Computer science,Dissipation,Parallel computing,Response time,Electronic engineering,Computer hardware,Cellular array,Low-power electronics
Conference
ISSN
ISBN
Citations 
1087-4852
0-7695-1242-9
0
PageRank 
References 
Authors
0.34
1
3
Name
Order
Citations
PageRank
Kyung-Saeng Kim171.31
KwangMyoung Rho200.34
Kwyro Lee326570.73