Name
Abstract | ||
|---|---|---|
With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten development period and reduce the power consumption. To this end, the compiler for a multi core processor is expected not only to parallelize program effectively, but also to control the voltage and clock frequency of processors and storages carefully inside an application program. This paper proposes a compilation scheme for reduction of power consumption under the multigrain parallel processing environment that controls Voltage/Frequency and power supply of each processor core on a chip. In the evaluation, the OSCAR compiler with the proposed scheme achieves 60.7 percent energy savings for SPEC CFP95 applu without performance degradation on 4 processors, and 45.4 percent energy savings for SPEC CFP95 tomcatv with real-time deadline constraint on 4 processors, and 46.5 percent energy savings for SPEC CFP95 swim with the deadline constraint on 4 processors. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/978-3-540-69330-7_25 | LCPC |
Keywords | Field | DocType |
processor core,multi core processor,spec cfp95,multi core processor architecture,percent energy saving,oscar compiler,spec cfp95 tomcatv,power supply,power consumption,compiler control power,spec cfp95 applu,chip,real time | Computer science,Power control,Parallel computing,Chip,Multiprocessing,Compiler,Spec#,Multi-core processor,Energy consumption,Clock rate,Embedded system | Conference |
Volume | ISSN | ISBN |
4339 | 0302-9743 | 3-540-69329-7 |
Citations | PageRank | References |
17 | 1.75 | 13 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jun Shirako | 1 | 433 | 34.56 |
| Naoto Oshiyama | 2 | 19 | 2.35 |
| Yasutaka Wada | 3 | 72 | 11.19 |
| Hiroaki Shikano | 4 | 28 | 4.90 |
| Keiji Kimura | 5 | 120 | 23.20 |
| Hironori Kasahara | 6 | 285 | 44.35 |