Name
Title | ||
|---|---|---|
A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization |
Abstract | ||
|---|---|---|
A highly linear LNA is implemented in a 0.18 μm SOI CMOS process for 1 GHz SAW-less receiver applications. To achieve lower noise figure (NF) than conventional simultaneous noise and input matching methods, a capacitive loading based simultaneous noise and input matching technique reducing the NF degradation coming from a lossy gate inductor has been devised. In addition, in order to improve both the 1 dB gain compression point (CP1dB) and the third-order intercept point (IP3) without sacrificing NF, a large-signal transconductance linearization method adopting body-bias control and complementary-superposition is proposed. The proposed LNA shows a measured input-referred CP1dB of 3 dBm, 1 dB desensitization point (B1dB) of 0 dBm and IB (in-band)-IIP3 of 22 dBm with gain of 10.7 dB and NF of 1.3 dB at 1 GHz while driving a 50 Ω load impedance. It draws 20 mA with a buffer stage from a 2.5 V supply voltage. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/JSSC.2014.2319262 | J. Solid-State Circuits |
Keywords | Field | DocType |
cmos analogue integrated circuits,body-bias control,input matching methods,third-order intercept point,lna,capacitive loading based simultaneous noise,noise figure 1.3 db,blocker,highly linear nf cmos low-noise amplifier,buffer stage,noise matching,current 20 ma,gain 1 db,operational amplifiers,complementary-superposition,noise figure,current 2.5 ma,mgtr,nf degradation,gain 10.7 db,uhf integrated circuits,lossy gate inductor,large signal,gain compression point,size 0.18 mum,silicon-on-insulator,saw-less,nonlinearity,high linearity,simultaneous matching,large-signal transconductance linearization method,frequency 1 ghz,resistance 50 ohm,complementary transconductance linearization,cmos,saw-less receiver,intermodulation distortion,soi cmos process,uhf amplifiers,transistors,noise,silicon on insulator,third order intercept point,logic gates,noise measurement,impedance,impedance matching | Low-noise amplifier,Noise measurement,Control theory,Computer science,Noise figure,Electronic engineering,Y-factor,Noise temperature,Transconductance,Effective input noise temperature,Gain compression | Journal |
Volume | Issue | ISSN |
49 | 6 | 0018-9200 |
Citations | PageRank | References |
5 | 0.65 | 12 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bum-Kyum Kim | 1 | 5 | 1.32 |
| Donggu Im | 2 | 53 | 8.36 |
| Jae-Young Choi | 3 | 783 | 110.19 |
| Kwyro Lee | 4 | 265 | 70.73 |